Optionality / moonshot: Wearable or Satellite Communications?
Allenby - June 2022 - page 27:
There is the possibility that future Gross Margins could be significantly higher, for example, if an EnSilica designed ASIC is taken by a client on a royalty basis and is sold in large quantities then this could provide a near 100% gross margin revenue stream running for several years. This scenario is not currently in our forecasts. |
Could someone explain the order and delivery process for a chip order?
For instance, the Siemens order that has passed tape-out has a delivery scheduled for Q2 2025.
The total contract value is $30 million over seven years. Does TSMC produce $4.2 million worth of chips once a year? Wouldn't it be more cost-effective to produce the full $30 million in a single print run rather than conducting seven separate runs? |
Afternoon Yump,
15x 25 and then 15x 26 as they prove each year up.
AST is a big part of proving it up. Chip goes into space in Q1 25 for the first time. Deliveries end Q4, early Q1? |
What do you think about the prospects here? |
Bloomberg - 16/10/24
The Cellular Space Race
AST SpaceMobile President Scott Wisniewski discusses the company's network expansion plan, taking on the likes of SpaceX. He speaks with Ed Ludlow and Caroline Hyde on "Bloomberg Technology." |
FT on the budget - 25/10/24:
The current system of tax credits for research and development will be maintained. |
Wonder if these two supply orders came through Quantum Leap?
15/7/24
EnSilica PLC New Supply Order for Edge AI Chip
28/2/24
EnSilica PLC Significant c.US$20 million Supply Win
"The ASIC design market is traditionally used by two very different types of organisation: the very established players, such as large industrial and automotive Tier 1s; and start-ups and very niche companies looking to put their ideas into silicon and have real market differentiation.
We are experienced in working with both types of business. This move helps us to also reach the potential market that lies between these two disparate groups. QLS has a fantastic track record in achieving this - for example with Dialog Semiconductor, before its recent acquisition by Renesas, where they enabled the Dialog to forge even more high value partnerships with customers. We’re obviously delighted to have them onboard.”
-Peter Juetter, 30/6/22. |
Simon Gordon, thanks for the Prof G Youtube link, very interesting. |
No trading update since May when the company raised it's full year revenue from £22.9m to £25m , which will be a record.
Forecast for the current to 31/05/2025 is:
Revenues in excess of £30 million and EBITDA in excess of £5.0 million for FY25. |
Just think how quickly that report could ping between those satellites though ;) |
I hate mobiles so probably more frustrated than most people ! Also work on a laptop half the day which is a relief. Goodness knows what will be said in 50 years about the effects of walking around staring at a tiny screen all the time ! Some sort of spatial skills disability I reckon, after an expensive commissioned report. |
Excellent overview on the chip scene starts at the 18-minute mark:
Prof G Show - 24/10/24
Nvidia’s Rise, Intel’s Fall, and the Chips in Between — ft. Patrick Moorhead
Patrick Moorhead, CEO and Chief Strategist of Moor Insights and Strategy, joins the show to break down the state of play in the chip industry. He explains how Intel lost its lead, discusses what makes Nvidia such a dominant company, and shares different investment opportunities in and around the semiconductor industry.
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Yump,
Apologies if the posts are interrupting your mobile scrolling experience. I typically work from a laptop and create posts with that perspective in mind. Each post varies, but if there's interesting information that enhances the story, I make sure to include it. |
Your digging is very helful but could you link to these articles with a summary.
On a mobile there’s a lot of scrolling between posts. |
 Growth Company Investor - 18/9/24
Question from the audience:
"What is the typical amount the customer pays, and how much do you cover?"
Mark Hodgkins:
"Well, it varies, and we have the option to refuse to pay anything if we choose. However, if we refuse, the customer might look for alternatives. On average, we cover around 15% of the cost. If the design cost is particularly high, we tend to contribute less. For example, we recently announced a large telecom order from a European company, valued at $17.5 million. About half of that will be recognized this year, with the other half next year. In that particular case, the customer is covering 95% of the cost. Now, just as a point of clarification, we evaluate each customer’s creditworthiness. A company like Siemens, which is very stable, would receive better terms. In this case, we might require around 20% up front. If we take on more of the financial responsibility, we can charge a higher price later in the supply stage, allowing us to recover the costs—though it may take some time."
ENSI RNS -2/9/24
This Contract finalises the preliminary terms of an agreement originally announced on 22 December 2023, with the total value, including NRE (non-recurring engineering) and supply, projected to exceed US$30 million over a ten-year period, based on quoted NRE fees and the Client's projected production volumes.
The NRE activities commenced in January 2024 with an initial specification phase, and have now progressed to the main design phase. The NRE fees for this phase are expected to significantly contribute to the Company's revenues for the current financial year, underpinning market expectations, with the production and supply phase of the ASICs expected to begin during 2027.
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ChatGPT:
The cost of designing a microchip can vary widely depending on its complexity, technology node, and application. For the most advanced microchips, such as those designed using cutting-edge process nodes like 3nm or 5nm, the cost can be extremely high due to the complexity of the design and the need for state-of-the-art fabrication technology.
Here’s a breakdown of the highest cost scenarios:
1. Advanced Technology Nodes (3nm, 5nm, etc.):
-Cost range: Designing a high-performance microchip at these nodes can cost $500 million to over $1 billion.
-Key factors: These costs come from design complexity, verification, testing, and the need for advanced electronic design automation (EDA) tools. Additionally, licensing IP (intellectual property) blocks for specific functionalities, and the expensive prototyping and manufacturing costs associated with advanced fabs contribute significantly.
2. High-end ASICs (Application-Specific Integrated Circuits):
-Cost range: For custom ASICs designed for specific industries (such as autonomous vehicles or 5G infrastructure), costs can be in the range of $50 million to $200 million.
-Key factors: ASICs often require significant custom design work and verification, as well as a long development cycle, contributing to the high cost.
3.FPGA to ASIC conversion:
-Cost range: If converting a field-programmable gate array (FPGA) design to an ASIC for mass production, costs can range from $10 million to $50 million depending on the complexity of the chip.
-Key factors: This type of conversion requires design refinement, additional testing, and specialized production methods.
4. Older Technology Nodes (28nm, 65nm, etc.):
-Cost range: For chips designed at older technology nodes, which are still widely used in some industries, design costs are significantly lower, ranging from $10 million to $50 million.
-Key factors: These chips are less expensive to design because the tools, IP, and manufacturing processes are well-established and cheaper.
The most expensive designs typically come from industries that demand extreme performance, like data centers, AI processors, GPUs, and advanced mobile processors. The costs will also increase depending on the number of design iterations, testing cycles, and level of customization.
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The EU may be helping fund some of the chip design:
ENSI RNS - 26/9/24
This partnership between EnSilica and SIAE MICROELETTRONICA is the base of a successful project output, representing a very critical part of the overall IPCEI EMISPHERE project, which is a key element for SIAE MICROELETTRONICA's plan for growth of technological solutions and expansion into new markets", said Stefano Poli, SIAE MICROELETTRONICA Group Managing Director.
SM press release - 11/4/24
SIAE MICROELETTRONICA OFFICIALLY SIGNED THE CONCESSION DECREE ISSUED MIMIT (ITALIAN MINISTRY OF INDUSTRY) ON EMISPHERE PROJECT
On 11 April 2024 SIAE MICROELETTRONICA officially signed the concession decree issued by the Italian authorities (MIMIT, Italian Ministry of Industry) on EMISPHERE project, part of IPCEI ME/CT - Microelectronics and Communication Technology – the Italian IPCEI Microelettronica 2 program. The milestone represents the successful conclusion of the award process and formalizes the start of operations on one of the most significant future development program for SIAE MICROELETTRONICA.
The program, sponsored by the European Community to support research, innovation and the industrial diffusion of microelectronics and communication technologies, will be financially supported by the company with 180 million Euro investment plan over the next five years.
SIAE MICROELETTRONICA is one of the four Italian companies selected as recipients of the IPCEI funds, being able to receive state aid to sustain the multi-years program aimed to develop a new generation of radio products for the mobile communications industry.The company is improving the European value chain with in-house development of innovative modem chips, microwave components and the antennas to enable the next generation microwave radio links to reach 100 Gbit/s transport capacity in the W and D band. |
The Yanks are on a different investing planet:
AST Space Odyssey - 4/10/24
Top 3 Reasons to Buy and Hold $ASTS, AST Space Mobile Unfurling News, Space X's insane FCC filing
Welcome to the first Episode of the AST Space Odyssey Podcast. Today we talk about Abel's recent tweet regarding the first Bluebirds unfurling, Space X's insane FCC filing calling $ASTS a meme stock, and the top 3 reasons to buy and hold $ASTS stock. |
Thanks, did wonder if it was the panels that gave the size. |
When the Block 2 sattelite unfolds it’s Solar panel sails they will cover 2400sqft, twice the size off the first five sattelites and 10 times as powerful. |
"each as large as a football field"???? |
 Mark Hodgkins - 18/9/24
Ian Lankshear, our CEO, unfortunately, can't be here today. When he left Hitachi in the late 1990s, he was working on radio frequency technology. Since then, we've been involved in mobile telecommunications for 23 years, giving us substantial experience in the field.
In 2018, the European Space Agency approached us to design a beam-forming technology for vehicles. Their goal was to ensure that all cars could be connected to the internet constantly, a necessity for future driverless cars, which require uninterrupted connectivity. You've likely heard about low Earth orbit satellite constellations—;these are part of the infrastructure that would support such connectivity. We were tasked with designing a beam-former, which is essentially a steerable antenna. This device, mounted on the roof of a vehicle, adjusts to maintain a satellite signal no matter where the car travels, ensuring reliable communication.
Our work on this project received positive peer reviews, and it led to a collaboration with an American company you may have seen in the news recently. They selected us based on the technology we had developed for the beam-former. Their plan is to launch 160 satellites into orbit next year, each as large as a football field. With our help, they aim to make it possible for anyone, anywhere in the world, to call anyone else using just their regular phone, as long as they've paid their monthly bill to their provider.
This collaboration has been transformational for us. Our chip, though just one among 600 in each satellite, is crucial—itR17;s what makes the whole system work. As a result of this success, the European Space Agency came back to us with another request: to design a companion chip for the one we had already developed, and they covered the entire design cost. We already have a customer for this new technology, and it’s in progress. Satellite communications have become a vital part of our business.
Another key area for us is our intellectual property (IP). Some of the IP we've developed for satellite communications is cutting-edge, and no one else has quite the same technology. Of course, competitors are working on similar things, and we expect competition, but our IP gives us a significant lead in the field. The contract with our American partner will be highly profitable for us next year. |
Thanks for sharing that! I do love computing and engineering history and the origins of phrases, sometimes lost in the modern world."Bug" is another great one that has never gone away. I struggle with "End User Compute" at work and show my age when I still call it "desktop support"! |
On case anyone wonders: The term "tape-out" is used in chip design to signify the completion of the design phase and the start of manufacturing. Originating from older days when the final design was written onto magnetic tape and sent out for fabrication, the term has endured as a symbolic milestone. |
 AST Earnings Call - 15/8/24
Abel Avellan
During the last few months, we shifted our manufacturing focus to increase Block 2 production, incorporating the lesson learned from manufacturing of the first five commercial satellites.
We are continue planning and initial production for the first 17 Block satellites to rebuilding phases within the initial launch in Q1 of 2025. These satellites, when equipped with our ASIC will be approximately 2,400 square feet in size and are expected to support up to 10 fold improvement of processing bandwidth per satellite compared to Block 1 satellite that we are launching this September. We expect to start using our ASIC on our six Block 2 satellite and we can use existing FPGA configuration for as long as it's required.
Alongside this activity, we have not lost sight of our technology roadmap. We can now report that we have completed the ASIC chip tape out with the S&C. This technology is the cornerstone of our Bloomberg Block 2 programs. The AST5000 ASIC is a novel, constant low power architecture developed to enable up to a 10 fold improvement in processing bandwidth on each satellite, unlocking opportunity for seamless Space-Based cellular broadband services worldwide. With the 3 bits per hertz that we have demonstrated using BlueWalker 3 and our planning commercial satellite capacity of up to 40 megahertz per beam, this translating to performance of up to 120 megahertz peak data rates.
The completion of the tape out is a milestone that marked the culmination of five years of dedicated research, development and engineering expertise with approximately 45 million all developed. In summary, we want to change the world.
We're seeking to connect the billions of people who are not connected, improving public safety, enabling global commerce and for the average user who can see fewer drop calls, frustrating dead zones and missing connections. This has not been easy, as we enter a new phase for our company and deeply proud of the team we have assembled and confident in the plan ahead of us.
Q&A
Chris Quilty: Also, just back to the ASIC, I mean, is it fair to assume that the ASIC production or delivery into production is sort of the gating factor for -- scaling up to the full Block 2 satellites?
Abel Avellan: No, Chris. I mean, the size of the satellite, the 2,400 square feet, the largest size for Block 2 is independent, if they are equipped with FPGA or ASIC. We have completed the ASIC FPGA tape out. The first launches will be still on an FPGA configuration, but we can keep launching on FPGA for as long as is needed. So there is not a prerequisite for launches. But of course, we want to incorporate the ASIC as that is a 10x increase in capacity per satellite. And we're very happy to conclude the tape out. It's -- we received the first dive several weeks back, and we're incorporating into our micron design as we continue to build the next batch of satellites. |
 Allenby - 2/9/24
In an August 2024 press release AST noted its ASIC (AST5000) had completed its tape out phase with TSMC, is expected to support up to 10x improvement of processing bandwidth per satellite and had a development cost of $45m. Although not confirmed by either company, our assumption is that AST5000 is the EnSilica designed ASIC.
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AST - 14/8/24
ASIC chip tape-out phase completed with TSMC, expected to support up to 10x improvement of processing bandwidth per satellite.
AST5000 ASIC is a novel, custom and low-power architecture developed over five years and approximately $45 million of development cost.
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Business Wire - 27/3/24
AST SpaceMobile ASIC Chip Enters Tape-Out Phase in Collaboration with TSMC
AST SpaceMobile, Inc. (“AST SpaceMobile”) (NASDAQ: ASTS), the company building the first and only space-based cellular broadband network accessible directly by everyday smartphones designed for both commercial and government use, proudly announces the commencement of the tape-out phase for its Application-Specific Integrated Circuit (ASIC), in collaboration with TSMC, the world's leading foundry.
As the cornerstone of AST SpaceMobile's BlueBird Block 2 program, the AST5000 ASIC is a novel, custom and low-power architecture developed to enable up to a tenfold improvement in processing bandwidth on each satellite, unlocking opportunities for seamless space-based cellular broadband services worldwide. This significant milestone marks the culmination of over four years of dedicated research, development, and engineering expertise, equivalent to an estimated 150 man-years of intensive work, as well as approximately $45 million of development.
"The commencement of the tape-out process for our ASIC, in collaboration with TSMC and other leaders in the semiconductor industry, is a testament to the unwavering commitment of our talented team," said Abel Avellan, Chairman and CEO of AST SpaceMobile. “As we advance towards the orbital launch of our Block 1 BlueBird satellites in the upcoming months, we are simultaneously making steady progress on the technology underlying our Block 2 satellites. This achievement underscores our relentless pursuit of innovation to address the growing demand for global connectivity, With the ASIC at the heart of our Block 2 program, we are a big step closer to ushering in a new era of satellite communications, helping to empower people with reliable connectivity, regardless of their location.”
AST SpaceMobile has achieved 3 Bits/Hertz using BlueWalker 3 and has planned capacity of up to 40 MHz per beam on its commercial satellites, which is planned to support 120 Mbps peak data rates. With our planned ASICs and 2,400 sq ft BlueBird satellite size, we expect to support up to 10,000 MHz of processing bandwidth per satellite in the future to enable the first and only space-based cellular broadband network. |
The people that get rich off of patents are patent lawyers. Though the first leg, search, may get eliminated by AI. |
150 billion transistors in 1 sq mm !!
The moon landing disbelievers need to get up with events. |