Building on its award-winning large-radix
(256-lane) CXL and PCIe "Apollo" Switch, XConn is poised to drive
UALink switch innovation for emerging AI ecosystem
SANTA CLARA,
Calif., Nov. 12, 2024 /PRNewswire/ -- XConn
Technologies (XConn), the innovation leader in next-generation
interconnect technology for the future of high-performance
computing and AI applications, today announced it has joined the
Ultra Accelerator Link™ (UALink™) Consortium as a Contributor
member. The newly incorporated UALink Consortium aims to establish
an industry-standard, high-speed interconnect to enable scale-up
communications between AI accelerators and switches, delivering low
latency and high bandwidth for AI workloads in data center
environments.
XConn's participation in the UALink Consortium
follows its successful introduction of the "Apollo" switch, a
pioneering 256-lane CXL and PCIe switch fabric architecture, which
has set new standards for scalability and flexibility in data
center interconnect solutions. Leveraging this large-radix
architecture, XConn is uniquely positioned to contribute to the
development of UALink's high-performance interconnect, which will
play a critical role in supporting the expanding needs of AI and
HPC workloads.
"We are thrilled to contribute to the development
of an open standard that directly addresses the high-performance
needs of AI infrastructures," said Gerry
Fan, CEO of XConn Technologies. "Our award-winning
large-radix Apollo switch architecture positions XConn as a leading
force in enabling the scale and efficiency required for the UALink
ecosystem. We look forward to working with industry leaders to
build a comprehensive ecosystem that empowers future AI deployments
and fosters scalable innovation across data centers."
The UALink Consortium was established by a
coalition of leading technology companies, including AMD, Amazon
Web Services (AWS), Astera Labs, Cisco, Google, Hewlett Packard
Enterprise (HPE), Intel, Meta, and Microsoft. The Consortium's
members are engaged to help shape and refine the UALink 1.0
specification, which will be available for review by Consortium
members this year and for general release in Q1 2025. The UALink
1.0 specification is designed to support high-speed data transfer
of up to 200Gbps per lane and can connect up to 1024 accelerators
within an AI pod. This enables data centers to achieve the
efficiency and scalability required for large AI models and
compute-intensive applications.
"We are pleased to welcome XConn Technologies as
a Contributor member," said Willie
Nelson, President of the UALink Consortium. "With their
expertise in interconnect technology, XConn brings a valuable
perspective to our mission of developing an open, high-performance
standard that can meet the demands of emerging AI and
high-performance computing applications."
More information on the UALink Consortium, which
announced its incorporation last month, is available at
www.ualinkconsortium.org.
About XConn Technologies
XConn
Technologies Holdings, Inc. (XConn) is the innovation leader in
next-generation interconnect technology for high-performance
computing and AI applications. The company is the industry's first
to deliver a hybrid switch supporting both CXL 2.0 and PCIe Gen5 on
a single chip. Privately funded, XConn is setting the benchmark for
data center interconnect with scalability, flexibility and
performance. For more information visit: xconn-tech.com.
About Ultra Accelerator Link
Consortium
Ultra Accelerator Link (UALink) is a high-speed,
scale-up accelerator interconnect technology that advances
next-generation AI cluster performance. AMD, Astera Labs, AWS,
Cisco, Google, HPE, Intel, Meta and Microsoft formed an open
industry standard body, Ultra Accelerator Link Consortium, to
develop technical specifications that facilitate breakthrough
performance for emerging usage models while supporting an open
ecosystem for data center accelerators.
Media Contacts:
Steve Sturgeon
Avista PR
ssturgeon@avistapr.com
858.472.5669
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SOURCE XConn Technologies
