Synplicity (MM) (NASDAQ:SYNP)
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Synplicity®, Inc.
(Nasdaq:SYNP), a leading supplier of innovative IC design and
verification solutions, today announced that its Synplify®
Premier software has been enhanced to provide more time-to-market
benefits to designers using high-density FPGAs. In release 9.0, the
company’s award winning(1) graph-based
physical synthesis technology has been optimized for Xilinx Virtex-5
FPGAs to deliver exceptional timing closure, analysis and debug for
these advanced devices. This latest release extends the graph-based
physical synthesis technology which has been implemented for Xilinx
Spartan-3, Virtex-II Pro and Virtex-4 FPGAs for more than two years.
Synplicity also announced it has extended these benefits to FPGA
designers targeting Altera Stratix-III, Stratix-II and Stratix-II GX
FPGAs, through the company’s Synplify Premier
Beta Program.
Unlike other solutions, Synplify Premier 9.0 gives users the most
accurate timing information and insight into debug performance-related
issues immediately following synthesis. Designers won’t
have to go through the hours of place and route, typical in traditional
flows, to get detailed timing information. Once the designer is happy
with the results, placement from the Synplify Premier software is passed
to place and route to ensure deterministic results and thus the fastest
timing closure. In addition to providing an optimal solution for timing
closure, Synplify Premier 9.0 provides several algorithmic QoR
enhancements and productivity boosting features such as a new user
interface, additional SystemVerilog constructs and a new module
generation capability.
Andy Haines, senior vice president of marketing at Synplicity notes, “The
Synplify Premier Platform is a comprehensive environment for FPGA design
comprising a variety of tools and technologies that provide improvement
in analysis, DSP implementation, debug and productivity needed to
successfully complete today’s high-density
designs. We worked very closely with our FPGA partners to ensure that
Synplify Premier 9.0 supports the intricate architectural elements of
these advanced 65-nanometer devices. We are excited to offer graph-based
physical synthesis to Virtex-5 designers through Synplify Premier and to
Stratix-III designers through our Beta Program.”
Robust FPGA Design Platform Integrates a Variety of Features
Synplicity continuously works to expand the breadth of its synthesis
technology to provide the most robust platform for FPGA implementation
and design. The Synplify Premier Platform is a complete environment
offering a range of features including RTL analysis, source-level debug,
HDL analysis, advanced floorplanning, physical analysis, module
generators and optimizations for DSP design. The Synplify Premier
solution is also a platform for implementation and debug of ASIC and SoC
prototypes using a single FPGA.
With the release of Synplify Premier 9.0, Synplicity offers additional
features for improved productivity. For example, Synplicity has expanded
its SynCore IP generator to support FIFOs in addition to RAMs. Designers
supply parameters to indicate the size and type of RAM or FIFO and the
IP generator wizard automatically creates technology independent RTL
ready for synthesis into an FPGA. These features allow designers to
avoid handwriting RTL or using technology dependent memory
instantiations for these functions.
Additionally, Synplicity continues to extend its support for the
SystemVerilog language. New SystemVerilog features in release 9.0
include:
Array assignments (packed & unpacked)
Arrays as arguments to functions, tasks and modules
Declarations in for-loop
Port declarations for multiple dimensions
Default argument types
Argument by names
Graph-Based Physical Synthesis Key to Addressing Timing Closure
In order to fully address timing closure, designers must have highly
accurate timing correlation between what a tool estimates and the final,
actual timing. The only proven way to get this timing correlation is to
perform detailed placement and routing during logic optimization and
also to have access to FPGA-specific routing information (routing graph
a.k.a. graph-based). Synplicity’s
graph-based physical synthesis is the only product on the market that
performs final detailed placement of logic during optimization, and
therefore, is the only tool that successfully addresses timing closure.
Actual testing on customer designs has shown that graph-based physical
synthesis provides timing correlation within 10 percent of final
post-route timing on over 90 percent of designs resulting in fewer
design iterations, less time to completion, and logical and physical
optimizations on the actual critical paths of the design.
Unlike other solutions, Synplicity’s
patented, and award-winning graph-based physical synthesis technology
merges logic optimization, placement and routing estimates into a single
process which is used alongside a highly accurate interconnect timing
graph (database) to help ensure a design’s
critical paths use the fastest available routing resources in the target
device. This is the only physical synthesis solution that creates
detailed placement for all logic which is then passed on to the vendor
tool for final routing.
“The new Synplify Premier product highlights
the ongoing benefits of the strong relationship between Xilinx and
Synplicity and their work in the Ultra High-Density Task Force. It also
signifies Synplicity’s ongoing commitment to
supporting the advancing requirement of FPGA devices,”
said Hitesh Patel, director of Software Product Marketing at Xilinx. “While
the architecture in the Virtex-5 devices provides the industry with
clear advantages for ultra-high density design, it did require close
attention by Synplicity to marry these benefits with its FPGA design
platform. The company came through with a solid solution that not only
provides new productivity benefits, but also addressed our primary
requirement for improved timing closure.”
New Algorithmic Changes Improve Performance, Area and Cost
Synplify Premier 9.0 is enhanced with algorithmic changes supporting the
sophisticated architectural and routing structures for improved
performance and area utilization reducing device cost. The huge capacity
of 65-nanometer devices, coupled with new architectural features,
complex routing and high-capacity memory structures can achieve even
greater quality of results through the use of specialized synthesis
tools with customized algorithms. Synplicity’s
physical synthesis software features a unique direct-mapping technology
employing a variety of sophisticated new heuristics tailored to minimize
the number of logic elements used while still meeting timing objectives.
ASIC Prototyping with FPGAs
As ASIC designers increasingly depend upon FPGAs to prototype all or
part of their designs, there is a need for a synthesis and verification
environment that can take HDL code written for an ASIC and efficiently
implement it in an FPGA. The Synplify Premier platform accommodates this
by performing automated gated-clock conversion handling of generated
clocks and Synopsys DesignWare® components.
Synplify Premier software addresses single FPGA prototypes, while
Synplicity’s Certify®
RTL prototyping product enables multiple FPGA prototypes with advanced
partitioning and pin multiplexing technology.
Pricing and Availability
Synplify Premier 9.0 is now available. Pricing for the design
environment starts at $54,000 (USD). Synplify Premier software customers
who are on active maintenance will receive the 9.0 release at no extra
cost. Designers interested in participating in the Beta Program, please
contact your Synplicity sales representative. For more information,
visit Synplicity’s Web site at http://www.synplicity.com.
About Synplicity
Synplicity®, Inc.
(Nasdaq:SYNP) is a leading supplier of innovative IC design and
verification solutions that serve a wide range of communications,
military/aerospace, semiconductor, consumer, computer, and other
electronic applications markets. Synplicity’s
FPGA implementation tools provide outstanding performance, cost and
time-to-market benefits by simplifying, improving and automating logic
synthesis, physical synthesis, analysis and debug for programmable logic
designs. Synplicity’s ESL synthesis solutions
significantly improve productivity for DSP designs realized in ASIC and
FPGA devices. The Confirma™ at-speed
verification platform, comprising software tools and the HAPS™
family of prototyping systems, enables both comprehensive verification
of ASIC, ASSP and SoC designs and software development prior to chip
tapeout. Synplicity is the number one supplier of FPGA synthesis tools
and its physical synthesis and ASIC verification technologies are the
recipients of several prestigious industry awards. The company operates
in more than 20 facilities worldwide and is headquartered in Sunnyvale,
California. For more information visit http://www.synplicity.com.
Forward-looking Statements
This press release contains forward-looking statements including, but
not limited to, statements regarding the performance, achievements and
benefits of the Synplify Premier software. In some cases, you will be
able to identify forward-looking statements by terminology such as “may,”
“will,” “should,”
“expects,” “can,”
“believes” or the
negative of these terms or other comparable terminology. These
statements are only predictions and involve known and unknown risks,
uncertainties and other factors that may cause the actual results to
differ materially from the forward-looking statements and changing
technical requirements and customer demands in the FPGA and ASIC
markets. For additional information and considerations regarding the
risks faced by Synplicity, see its annual report on Form 10-K for the
year ended December 31, 2006 and the quarter report on Form 10Q for the
three months ended September 30, 2007, as filed with the Securities and
Exchange Commission, as well as other periodic reports filed with the
SEC from time to time. Although Synplicity believes that the
expectations reflected in the forward-looking statements are reasonable,
Synplicity cannot guarantee the future performance or achievements of
its software. In addition, neither Synplicity nor any other person
assumes responsibility for the accuracy or completeness of these
forward-looking statements. Synplicity disclaims any obligation to
update information contained in any forward-looking statement.
(1) Note: Synplify Premier with graph-based physical synthesis
won the 2006 LSI Design of the year award (Japan); also in 2006 it was a
finalist for the European Elektra Award; it was named one of EDN’s
top products of 2005; and was a finalist for the EDN Innovation
Awards and IEC DesignVision Award for 2005.
Synplicity, Synplify, and Certify, are registered trademarks of
Synplicity, Inc., HAPS, High-performance ASIC Prototyping System, and
Confirma, are trademarks of Synplicity Inc. All other names mentioned
herein are the trademarks or registered trademarks of their owners.